Capacitors are one type of component commonly used in the fabrication of integrated circuits, for example in DRAM circuitry. A typical capacitor is comprised of two conductive electrodes separated by a non-conducting dielectric region. As integrated circuitry density has increased, there is a continuing challenge to maintain sufficiently high storage capacitance despite typical decreasing capacitor area. The increase in density of integrated circuitry has typically resulted in greater reduction in the horizontal dimension of capacitors as compared to the vertical dimension. In many instances, the vertical dimension of capacitors has increased.
One manner of fabricating capacitors is to initially form an insulative material within which a capacitor storage node electrode is formed. For example, an array of capacitor electrode openings for individual capacitors is typically fabricated in such insulative capacitor electrode-forming material, with a typical insulative electrode-forming material being silicon dioxide doped with one or both of phosphorus and boron. The capacitor electrode openings are typically formed by etching. It can be difficult to etch the capacitor electrode openings within the insulative material, particularly where the openings are deep.
Further and regardless, it is often desirable to etch away most if not all of the capacitor electrode-forming material after individual capacitor electrodes have been formed within the openings. Such enables outer sidewall surfaces of the electrodes to provide increased area and thereby increased capacitance for the capacitors being formed. However, the capacitor electrodes formed in deep openings are typically correspondingly much taller than they are wide. This can lead to toppling of the capacitor electrodes, either during the etch to expose the outer sidewalls surfaces, during transport of the substrate, and/or during deposition of the capacitor dielectric layer or outer capacitor electrode layer. Our U.S. Pat. No. 6,667,502 teaches the provision of a brace or retaining structure intended to alleviate such toppling. Other aspects associated in the formation of a plurality of capacitors, some of which include bracing structures, are also disclosed and are:                U.S. Published Application No. 2005/0051822 A1;        U.S. Published Application No. 2005/0054159 A1;        U.S. Published Application No. 2005/0158949 A1;        U.S. Published Application No. 2005/0287780 A1;        U.S. Published Application No. 2006/0014344 A1;        U.S. patent application Ser. No. 10/928,931, filed Aug. 27, 2004, titled “Methods of Forming a Plurality of Capacitors”, naming Brett W. Busch, Fred D. Fishburn and James Rominger as inventors;        U.S. patent application Ser. No. 10/929,037, filed Aug. 27, 2004, titled “Methods of Forming a Plurality of Capacitors”, naming H. Montgomery Manning as inventor;        U.S. patent application Ser. No. 11/006,331, filed Dec. 6, 2004, titled “Methods of Forming Pluralities of Capacitors, and Integrated Circuitry”, naming Cem Basceri and Gurtej S. Sandhu as inventors;        U.S. patent application Ser. No. 11/083,489, filed Mar. 18, 2005, titled “Methods of Forming Pluralities of Capacitors”, naming Gurtej S. Sandhu and D. Mark Durcan as inventors;        U.S. patent application Ser. No. 11/131,552, filed May 18, 2005, titled “Methods of Forming Pluralities of Capacitors”, naming H. Montgomery Manning as inventor;        U.S. patent application Ser. No. 11/131,575; filed May 18, 2005, titled “Methods of Forming a Plurality of Capacitors, and Integrated Circuitry Comprising a Pair of Capacitors”, naming H. Montgomery Manning as inventor;        U.S. patent application Ser. No. 11/196,593; filed Aug. 2, 2005, titled “Methods of Forming Pluralities of Capacitors”, naming Gurtej S. Sandhu, H. Montgomery Manning and Stephen J. Kramer as inventors;        U.S. patent application Ser. No. 11/272,232, filed Nov. 10, 2005, titled “Methods of Forming a Plurality of Capacitor Devices”, naming H. Montgomery Manning, Thomas M. Graettinger and Marsela Pontoh as inventors; and        U.S. patent application Ser. No. 11/272,247, filed Nov. 10, 2005, titled “Methods of Forming a Plurality of Capacitor Devices”, naming H. Montgomery Manning, Thomas M. Graettinger and Marsela Pontoh as inventors;        
Typical fabrication of capacitors particularly common in memory circuitry forms an array of capacitors within a capacitor array area. Control or other circuitry area is typically displaced from the capacitor array area, with the substrate including an intervening area between the capacitor array area and the control or other circuitry area. In some instances, a trench is formed in the intervening area between the capacitor array area and the other circuitry area. Such trench can be formed commensurate with the fabrication of the openings within the capacitor array area within which the isolated capacitor electrodes will be received.
When etching the insulative electrode-forming material within which the capacitor electrodes are received to expose outer sidewall surfaces thereof, it is typically desired that none of the insulative material within the other circuitry area be etched. One prior art method restricts such by masking the peripheral circuitry area. Specifically, a silicon nitride layer is typically formed over the predominantly insulative material within which the capacitor electrodes are formed. The conductive material deposited to form the capacitor electrodes within the electrode openings also deposits and lines the trench between the capacitor array area and the peripheral circuitry area. A typical common conductive material is titanium nitride. The titanium nitride is polished back at least to the silicon nitride layer, thereby forming isolated container-shaped structures within individual capacitor electrode openings in the array area and within the trench. Accordingly, the sidewalls and bottom of the trench are covered or masked with titanium nitride, whereas the top or elevationally outermost surface of the peripheral or other circuitry area is covered with silicon nitride.
Etch access openings are then formed at spaced intervals within the silicon nitride within the capacitor array area to expose the insulative capacitor electrode-forming material there beneath. Elevationally outermost surfaces of the peripheral circuitry area are typically kept entirely masked with the silicon nitride layer. When the insulative capacitor electrode-forming material comprises phosphorus and/or boron doped silicon dioxide, a typical aqueous etching chemistry utilized to etch such highly selectively to titanium nitride and to silicon nitride is an aqueous HF solution. Such desirably results in exposure of the outer sidewalls of the individual capacitor electrodes while the peripheral insulative material remains masked from such etching by the overlying silicon nitride layer and from the titanium nitride within the peripheral trench.
Unfortunately, the titanium nitride from which the capacitor electrodes are formed and which masks the sidewalls of the peripheral trench can be deposited in a manner which produces cracks or pinholes that extend laterally therethrough. This is not particularly problematic within the capacitor array area as it is desired that the insulative material be removed from both the inner and outer lateral sidewalls of the capacitor electrodes. Passage of liquid etchant through any cracks or pinholes within the array area does not defeat this purpose. However, cracks or pinholes in the titanium nitride layer protecting the lateral sidewalls of the peripheral circuitry insulative material can be problematic. Specifically, etchant seeping therethrough can cause etching voids or pockets to form laterally within the peripheral circuitry insulative material. These can later create fatal contact-to-contact shorts in the peripheral circuitry area when conductive vertical contacts are formed therein.
One existing solution to such problem is to deposit a very thin polysilicon layer to line internal portions of the capacitor electrodes and against the titanium nitride layer which laterally covers the insulative material of the peripheral circuitry area. Polysilicon is highly resistant to etch by HF. Such will shield any pinholes, thereby precluding HF or other etchants from seeping therethrough and undesirably etching the peripheral circuitry area insulative material.
Polysilicon is typically undesired subsequently, and is therefore removed. Accordingly, after etching back the insulative material to expose the outer sidewalls of the capacitor electrodes, a dedicated wet etch is typically conducted to highly selectively remove the polysilicon relative to undoped silicon dioxide, the titanium nitride, and the silicon nitride. Prior to this, a separate dedicated wet etch is typically conducted to remove an undesired native oxide which forms over the polysilicon.
While the invention was motivated in addressing the above identified issues, it is in no way so limited. The invention is only limited by the accompanying claims as literally worded, without interpretative or other limiting reference to the specification, and in accordance with the doctrine of equivalents.